CDT I-BM API
1.0.0
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include
CdtBmRegsMap.h
1
#pragma once
2
3
#include <string>
4
#include <unordered_map>
5
6
#include "FrontEndBase.h"
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8
const
FENRegMap cdt_bm_register_map = {{
"status_base"
, 0x00000000},
9
{
"status_date"
, 0x00000006},
10
{
"status_incl"
, 0x00000007},
11
{
"status_config"
, 0x0000000A},
12
{
"status_clk_config"
, 0x0000000B},
13
{
"status_fifos_config"
, 0x0000000C},
14
{
"status_asics_config"
, 0x0000000D},
15
{
"status_rs_config"
, 0x0000000E},
16
{
"status_filter_config"
, 0x0000000F},
17
{
"status_hb_config"
, 0x00000010},
18
{
"status_adc_config"
, 0x00000011},
19
{
"status_no_of_hv_interfaces"
, 0x00000012},
20
{
"status_status"
, 0x00000014},
21
{
"status_uid"
, 0x00000015},
22
{
"status_uid_high"
, 0x00000016},
23
{
"status_uid_error"
, 0x00000017},
24
{
"status_ring_adr"
, 0x00000018},
25
{
"status_local_bus_error"
, 0x0000001A},
26
// HV registers
27
{
"hv_base"
, 0x00003400},
28
{
"hv_status"
, 0x00003404},
29
{
"hv_i2c_request"
, 0x00003408},
30
{
"hv_i2c_response"
, 0x0000340C},
31
{
"rb_base"
, 0x00000100},
32
{
"extra_base"
, 0x00000200},
33
{
"extra_testreg_dma_status"
, 0x00000201},
34
{
"extra_testreg"
, 0x00000202},
35
{
"extra_insert_data"
, 0x00000203},
36
{
"extra_cdce_locked_counter"
, 0x00000204},
37
{
"extra_jc_los_counter"
, 0x00000205},
38
{
"extra_freq_counter_stop"
, 0x00000206},
39
{
"fx2_base"
, 0x00000300},
40
{
"fx2_timeout_stop"
, 0x00000301},
41
{
"fx2_timeout_counter"
, 0x00000302},
42
{
"rs_base"
, 0x00001000},
43
{
"rs_gem_no"
, 0x00001001},
44
{
"rs_asic_channel"
, 0x00001002},
45
{
"rs_mask_data"
, 0x00001003},
46
{
"sim_base"
, 0x00001100},
47
{
"sim_memory_depth_bits"
, 0x00001101},
48
{
"sim_pause_length"
, 0x00001102},
49
{
"sim_zero_pattern"
, 0x00001103},
50
{
"sim_zero_pattern_adc"
, 0x00001104},
51
{
"sim_ram_adr"
, 0x00001105},
52
{
"sim_data_reg"
, 0x00001106},
53
{
"sim_adc_ram_adr"
, 0x00001107},
54
{
"sim_adc_data_reg"
, 0x00001108},
55
{
"sim_chopper_period"
, 0x00001109},
56
{
"sim_status"
, 0x0000110A},
57
{
"sim_data_reg_dma"
, 0x0000110C},
58
{
"rdc_base"
, 0x00001200},
59
{
"rdc_value"
, 0x00001201},
60
{
"rdc_dma_channel"
, 0x00001202},
61
{
"rdc_dma_value"
, 0x00001203},
62
{
"rdr_ffro_base"
, 0x00001300},
63
{
"rdr_ffro_status"
, 0x00001301},
64
{
"rdr_ffro_data_lost_counter"
, 0x00001302},
65
{
"rdr_ffro_timestamp"
, 0x00001303},
66
{
"rdr_ffro_data_reg"
, 0x00001304},
67
{
"rdr_cro_current_data"
, 0x00001306},
68
{
"rdr_cro_data"
, 0x00001305},
69
{
"rdr_albro_fifo_status"
, 0x00001307},
70
{
"rdr_albro_current_data"
, 0x00001308},
71
{
"rdr_albro_filtered_bytes_active"
, 0x00001309},
72
{
"rdr_albro_filtered_actives"
, 0x0000130B},
73
{
"rdr_albro_filtered_timestamp"
, 0x0000130C},
74
{
"rdr_albro_current_frame_timestamp"
, 0x0000130E},
75
{
"rdr_albro_written_bytes"
, 0x00001310},
76
{
"rdr_albro_filtered_addr_bytes"
, 0x00001311},
77
{
"filter_base"
, 0x00001400},
78
{
"filter_xsize"
, 0x00001401},
79
{
"filter_shift_x"
, 0x00001402},
80
{
"filter_mask_index"
, 0x00001403},
81
{
"filter_mask_list"
, 0x00001404},
82
{
"filter_data_lost"
, 0x00001406},
83
{
"filter_emi_corner"
, 0x0000140A},
84
{
"filter_emi_all"
, 0x0000140B},
85
{
"filter_emi_powtex"
, 0x0000140C},
86
{
"filter_xsingle"
, 0x0000140F},
87
{
"filter_xdouble"
, 0x00001410},
88
{
"filter_xtriple"
, 0x00001411},
89
{
"filter_xmultiple"
, 0x00001412},
90
{
"filter_xinvalid"
, 0x00001413},
91
{
"filter_xmultihit"
, 0x00001414},
92
{
"filter_xtime1"
, 0x00001415},
93
{
"filter_xtime2"
, 0x00001416},
94
{
"filter_xtime3"
, 0x00001417},
95
{
"filter_xtimem"
, 0x00001418},
96
{
"filter_xtimei"
, 0x00001419},
97
{
"filter_ysingle"
, 0x0000141A},
98
{
"filter_ydouble"
, 0x0000141B},
99
{
"filter_ytriple"
, 0x0000141C},
100
{
"filter_ymultiple"
, 0x0000141D},
101
{
"filter_yinvalid"
, 0x0000141E},
102
{
"filter_ymultihit"
, 0x0000141F},
103
{
"filter_ytime1"
, 0x00001420},
104
{
"filter_ytime2"
, 0x00001421},
105
{
"filter_ytime3"
, 0x00001422},
106
{
"filter_ytimem"
, 0x00001423},
107
{
"filter_ytimei"
, 0x00001424},
108
{
"filter_cor_unusedx"
, 0x00001428},
109
{
"filter_cor_unusedy"
, 0x00001429},
110
{
"filter_cor_ambix"
, 0x0000142A},
111
{
"filter_cor_ambiy"
, 0x0000142B},
112
{
"filter_cor_eventx"
, 0x0000142C},
113
{
"filter_cor_eventy"
, 0x0000142D},
114
{
"filter_cor_event2d"
, 0x0000142E},
115
{
"meas_base"
, 0x00001600},
116
{
"meas_reset"
, 0x00001601},
117
{
"meas_counting"
, 0x00001602},
118
{
"meas_abs_time_counter_stop_low"
, 0x00001603},
119
{
"meas_abs_time_counter_stop_high"
, 0x00001604},
120
{
"meas_chopper_counter_stop"
, 0x00001605},
121
{
"meas_event_counter_stop"
, 0x00001607},
122
{
"meas_ext_counter_stop"
, 0x00001608},
123
{
"meas_abs_time_counter"
, 0x0000160A},
124
{
"meas_chopper_counter"
, 0x0000160C},
125
{
"meas_event_counter"
, 0x0000160E},
126
{
"meas_ext_counter"
, 0x0000160F},
127
{
"mca_base"
, 0x00001500},
128
{
"mca_hysterese"
, 0x00001501},
129
{
"mca_event_counter"
, 0x00001502},
130
{
"md_base"
, 0x00001700},
131
{
"md_dump_period"
, 0x00001701},
132
{
"md_raw_data_lost"
, 0x00001702},
133
{
"md_chopper_lost"
, 0x00001703},
134
{
"md_neutron_lost"
, 0x00001704},
135
{
"md_adc_lost"
, 0x00001705},
136
{
"md_latency_data_pipe"
, 0x00001706},
137
{
"md_rdr_longer_pending"
, 0x00001707},
138
{
"md_neutron_fifo_count"
, 0x00001708},
139
{
"md_adc_mca_fifo_count"
, 0x00001709},
140
{
"ed_base"
, 0x00001800},
141
{
"ed_status"
, 0x00001801},
142
{
"ed_data_lost"
, 0x00001802},
143
{
"ed_status_2"
, 0x00001803},
144
{
"ed_data_reg"
, 0x00001804},
145
{
"cc_base"
, 0x00002000},
146
{
"cc_id"
, 0x00002001},
147
{
"cc_timeout_counter_stop"
, 0x00002002},
148
{
"cc_timeout_counter"
, 0x00002003},
149
{
"cc_data_in"
, 0x00002004},
150
{
"cc_data_out"
, 0x0000200C},
151
{
"csd_base"
, 0x00002100},
152
{
"csd_config_present"
, 0x00002102},
153
{
"csd_fw_pattern"
, 0x00002103},
154
{
"csd_index"
, 0x00002104},
155
{
"csd_delay"
, 0x00002105},
156
{
"csd_async_pattern"
, 0x00002107},
157
{
"csd_async_counter"
, 0x00002108},
158
{
"csd_fw_lost_counter"
, 0x00002110},
159
{
"cs_status"
, 0x00002101},
160
{
"cs_bitslip_modified_counter"
, 0x00002118},
161
{
"css_rawdata_lsbs"
, 0x00002120},
162
{
"css_rawdata_msbs"
, 0x00002128},
163
{
"pt2_write_user_sc_chain_ram"
, 0x0000200A},
164
{
"pt2_read_user_sc_chain_ram"
, 0x00002012},
165
{
"pt2_read_last_read_sc_chain_ram"
, 0x0000201A},
166
{
"pt2_measure_mode"
, 0x00002022},
167
{
"pt2_injection_discharge_cycles"
, 0x00002023},
168
{
"pt2_injection_switch_delay_for_measure_capacitance_cycles"
, 0x00002024},
169
{
"pt2_readout_clock_enable"
, 0x00002115},
170
{
"pt2_rawdata_slice_control"
, 0x00002200},
171
{
"pt2_rawdata_slice"
, 0x00002201},
172
{
"pt2_rawdata_dma"
, 0x00002202},
173
{
"pt2_rawdata_dma_index"
, 0x00002203},
174
{
"poldi_config_request_read_data"
, 0x00002005},
175
{
"poldi_config_request_write_sync"
, 0x00002006},
176
{
"poldi_config_test_light_duration"
, 0x00002007},
177
{
"poldi_config_test_light_meas_trigger_delay"
, 0x00002008},
178
{
"poldi_config_test_light_pwm_period"
, 0x00002009},
179
{
"poldi_sim_pulse_time"
, 0x00002205},
180
{
"dio_base"
, 0x00000400},
181
{
"dio_ext_input_index"
, 0x00000401},
182
{
"dio_dig_output_index"
, 0x00000402},
183
{
"dio_ext_output_index"
, 0x00000403},
184
{
"dio_length_output"
, 0x00000404},
185
{
"dio_no_of_dig_inputs"
, 0x00000405},
186
{
"dio_freq_counter_stop"
, 0x00000406},
187
{
"dio_other_pulse_mask"
, 0x00000407},
188
{
"aux_base"
, 0x00000500},
189
{
"aux_config_extern"
, 0x00000501},
190
{
"aux_status_serdes"
, 0x00000502},
191
{
"aux_bitslip_not_locked_counter"
, 0x00000503},
192
{
"aux_dig_valid_counter"
, 0x00000504},
193
{
"aux_dig_lost_sync_counter"
, 0x00000505},
194
{
"aux_dig_frame_err_counter"
, 0x00000506},
195
{
"aux_dig_code_err_counter"
, 0x00000507},
196
{
"aux_dig_decode_err_counter"
, 0x00000508},
197
{
"aux_com_timeout_stop"
, 0x00000509},
198
{
"aux_com_timeout_counter"
, 0x0000050A},
199
{
"aux_com_timeout_reset"
, 0x0000050B},
200
{
"aux_com_lost_sync_counter"
, 0x0000050C},
201
{
"aux_com_frame_err_counter"
, 0x0000050D},
202
{
"aux_com_code_err_counter"
, 0x0000050E},
203
{
"aux_com_decode_err_counter"
, 0x0000050F},
204
{
"cdce_config_start_flag"
, 0x00000600},
205
{
"cdce_config_write"
, 0x00000601},
206
{
"cdce_config_read"
, 0x00000602},
207
{
"cdce_config_recoveryclk_disabled"
, 0x00000606},
208
{
"adc_config_start_flag"
, 0x00000603},
209
{
"adc_config_write"
, 0x00000604},
210
{
"adc_config_read"
, 0x00000605},
211
{
"temp_config_status"
, 0x00000607},
212
{
"temp_config_write"
, 0x00000608},
213
{
"temp_config_read"
, 0x00000609},
214
{
"eprom_config_hwreset"
, 0x0000060B},
215
{
"eprom_config_write"
, 0x0000060C},
216
{
"eprom_config_read"
, 0x0000060D},
217
{
"eprom_config_cdrs_like_status"
, 0x0000060E},
218
{
"eprom_config_size"
, 0x0000060F},
219
{
"icap_base"
, 0x00000610},
220
{
"icap_config_write"
, 0x00000611},
221
{
"icap_config_read"
, 0x00000612},
222
{
"sfpdd_config_control"
, 0x00000613},
223
{
"sfpdd_config_status"
, 0x00000614},
224
{
"sfpdd_config_write_data"
, 0x00000615},
225
{
"sfpdd_config_read_data"
, 0x00000616},
226
{
"hb_base"
, 0x00003000},
227
{
"hb_dwell_time_stop"
, 0x00003001},
228
{
"hb_time_bin_stop"
, 0x00003002},
229
{
"hb_life_time_counter"
, 0x00003003},
230
{
"hb_latency_data_pipe"
, 0x00003005},
231
{
"hb_set_sram_adr"
, 0x0000300A},
232
{
"hb_event_counter"
, 0x0000300B},
233
{
"hb_data_lost_counter"
, 0x0000300C},
234
{
"hb_actual_sram_adr"
, 0x0000300D},
235
{
"hb_sram_data"
, 0x0000300E},
236
{
"hb_sram_data_incr"
, 0x0000300F},
237
{
"adc_peak_module_reset"
, 0x00003100},
238
{
"adc_peak_tapdebug"
, 0x00003101},
239
{
"adc_peak_startupcal_running"
, 0x00003102},
240
{
"adc_peak_too_high"
, 0x00003103},
241
{
"adc_peak_tapdata"
, 0x00003104},
242
{
"adc_peak_min"
, 0x00003105},
243
{
"adc_peak_midstable"
, 0x00003106},
244
{
"adc_peak_rawdata_low"
, 0x00003107},
245
{
"adc_peak_rawdata_high"
, 0x00003108},
246
{
"adc_peak_adc_fifostatus"
, 0x00003109},
247
{
"adc_peak_fifodata_low"
, 0x0000310A},
248
{
"adc_peak_fifodata_high"
, 0x0000310B},
249
{
"adc_peak_caldata"
, 0x0000310C},
250
{
"adc_peak_neg_threshold"
, 0x0000310D},
251
{
"adc_peak_peak_fifostatus"
, 0x00003115},
252
{
"adc_peak_datareg"
, 0x0000311D},
253
{
"adc_peak_peak_fifodepth"
, 0x00003125},
254
{
"adc_peak_calstatus"
, 0x00003126},
255
{
"pbfo_use_power_down_slots"
, 0x00003200},
256
{
"pbfo_dig_out"
, 0x00003201},
257
{
"pbfo_tx_ack_measurement_counter"
, 0x00003202},
258
{
"pbfo_dig_encode_error_counter"
, 0x00003203}
259
260
};
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